Instruction predication is a valuable feature in some processor architectures. Predication facilitates the prevention of execution of instructions in an instruction stream, which is referred to as “predicating” an instruction. Instruction predication is generally used in execution units performing algorithms that rely on loops and/or conditional branches and decision making. Instruction predication may be used, for example, in an algorithm utilizing a loop, where instructions implementing the loop are to be skipped when the loop is exited. As such, the instructions to be skipped when exiting the loop may be predicated in an instruction stream. In another example, a conditional instruction may have two possible outcomes, where instructions of one branch may be skipped depending on the resolution of the conditional instruction. As such, instruction predication logic predicates (i.e., prevents execution of) instructions corresponding to the branch not “taken” by the conditional instruction.
For example, image processing algorithms implemented in some three dimensional (3D) graphics applications incorporate a z-buffer algorithm test. In such 3D graphics applications, great care must be taken to avoid drawing objects that would not be visible, such as when an opaque object is closer to the camera than another object. In such a case, the object closer to the camera would block the farther object, and a 3D application that is attempting to draw this scene must not draw the further object. A z-buffer generally refers to a set of values that represent distance from the camera (sometimes called depth) for each pixel. Every time the rasterizing algorithm is ready to draw a pixel, it compares the depth of the pixel it is attempting to draw with the depth of the z-buffer for that pixel. If the z-buffer value indicates that the existing pixel is closer to the camera, the new pixel is not drawn and the z-buffer value is not updated. In contrast, if the new pixel to be drawn is closer to the camera, the new pixel is drawn and the z-buffer is updated with the new depth associated with that pixel. In a pixel shader of the 3D application, the algorithm may draw a pixel and update the z-buffer if the new pixel is closer to the camera than the older pixel stored in the z-buffer, but if the new pixel is not closer to the camera, the instructions following the z-buffer compare should be skipped and the next pixel should be tested. As such, predication may be utilized to skip instructions for a pixel depending on the outcome of the z-buffer compare.
In conventional processor architectures utilizing instruction predication, predication of an instruction is generally controlled by a state of a predication register. Each instruction in the instruction stream includes a predication register address portion corresponding to an address in the predication register, where the data stored at the register address indicates whether to predicate the instruction. As such, data of a predication register address may be adjusted to indicate whether to predicate an instruction, where the instruction will include data indicating the predication register address the processor may access to determine whether to predicate the particular instruction. For example, in the VLIW IA-64 processor architecture, a 64 bit predication register and 128 bit 3-instruction bundles are utilized, where each instruction includes a 41 bit instruction size and a predication field of 6-bits in the 41 bit instruction that determines which register address of the predication register is used to determine whether to predicate the instruction.
However, in some fixed instruction length processor architectures, using bits of an instruction for a predication field uses up valuable space in the instruction that otherwise may be used for register addresses, opcodes, and/or other such data. As such, in some processor architectures, and particularly smaller fixed length instruction architectures, utilizing bits of an instruction for a predicate field may reduce the number of possible opcodes, source and/or target addresses that may be utilized in a processor using the architecture.
Therefore, a continuing need exists in the art for implementing instruction predication in processor architectures, and desirably without dedicating bits of an instruction to a predication field.